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JUNE 2003
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
GENERAL DESCRIPTION
The XRD9836 is a precision 16-bit analog front-end (AFE) for use in 3-channel/1-channel CCD/CIS document imaging applications. Pixel-by-pixel gain and offset for each of the 3 channels are controlled using a time multiplexed parallel input. Offset and Gain are sequentially supplied for red, green, and blue. The outputs from each of the three channels are transmitted time multiplexed with the high order byte first followed by the low order byte for red, blue and green. FEATURES * 16-bit resolution ADC, 30MHz Sampling Rate * 10-bit accurate linear programmable gain range selectable as either 2-to-20 V/V or 1-to-10 V/V per channel
* Sampling rates from 1.0 MSPS to 10.0 MSPS per channel for 3 -Channel mode and up to 15.0 MSPS in single channel mode.
* Pixel-by-Pixel Offset and Gain control through a parallel
interface running at a maximum 60 Mbyte/sec. data rate
* A microprocessor serial port to control various modes of
operation
* Fixed Gain/Offset Mode (FGOM) or Pixel by Pixel Gain/
Offset Mode (PPGOM)
* Alternate Pixel Offset Adjust Mode (APOAM) * Low Power CMOS=280mW (typ. @ 3V); Power-Down
Mode=1mW (typ. @ 3V with static clocks)
* Single Power Supply (3.0 to 3.6 Volts) with Max CCD
input signal of 1V and reset pulse up to 0.5V
* Fully-differential input pins and internal path
* High ESD Protection: 2000 Volts Minimum APPLICATIONS * Scanners, MFP's
FIGURE 1. BLOCK DIAGRAM
IE
GRN+ REDRED+
GRNBLUE+ BLUE-
CAPP CAPN CMREF REXT BIAS
RED HIGH ORDER ADC OUT RED LOW ORDER ADC OUT
ANALOG INPUTS
RED GAIN REGISTER RED OFFSET REGISTER
Red Gain 10 10 Red Offset
RED CDS & PGA Green CDS & PGA BLUE CDS & PGA
XRD9836
M U X
16-BIT 30MHz ADC
16
OFFSET/GAIN INPUT 10
GREEN GAIN Green Gain REGISTER 10 10 GREEN OFFSET REGISTER Green Offset BLUE GAIN REGISTER BLUE OFFSET REGISTER
Blue Gain 10 10 Blue Offset
D E M U X
GREEN HIGH ORDER ADC OUT GREEN LOW ORDER ADC OUT BLUE HIGH ORDER ADC OUT BLUE LOW ORDER ADC OUT
8
ADC OUT
ADCLK SERIAL PORT SCLK SDATA LOAD TIMING VSAMP BSAMP LCLMP
3 3
POWER
2 2
Ognd Avdd Agnd Ovdd Dvdd Dgnd
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRD9836
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16-BIT PIXEL GAIN AFE
REV. 1.0.0
FIGURE 2. PIN OUT OF THE DEVICE
ADCLK VSAMP BSAMP LCLMP IE SCLK SDIO LOAD Ovdd Ognd Avdd RED RED+ GRN GRN+ BLU BLU+ Agnd Rext Agnd Avdd CMREF CAPP CAPN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Dgnd Dvdd OGI [0] OGI [1] OGI [2] OGI [3] OGI [4] OGI [5] OGI [6] OGI [7] OGI [8] OGI [9] ADCO [0] ADCO [1] ADCO [2] ADCO [3] Ognd Ovdd ADCO [4] ADCO [5] ADCO [6] ADCO [7] Agnd Avdd
TSSOP
ORDERING INFORMATION
PART NUMBER XRD9836ACG PACKAGE 48 - TSSOP OPERATING TEMPERATURE RANGE 0C to +70C
2
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XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
PIN DESCRIPTIONS
PIN #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SYMBOL
ADCLK VSAMP BSAMP LCLMP IE SCLK SDIO LOAD Ovdd Ognd Avdd REDRED+ GRNGRN+ BLUBLU+ Agnd REXT Agnd Avdd CMREF CAPP CAPN Avdd Agnd ADCO[7] ADCO[6] ADCO[5] ADCO[4] Ovdd Ognd ADCO[3] ADCO[2] ADCO[1] ADCO[0] OGI[9] OGI[8] OGI[7] OGI[6] OGI[5] OGI[4] OGI[3] OGI[2] OGI[1] OGI[0] Dvdd Dgnd
TYPE
clock clock clock clock digital clock digital in/out digital in power ground power analog analog analog analog analog analog ground analog ground power analog analog analog power ground output output output output power ground output output output output digital in digital in digital in digital in digital in digital in digital in digital in digital in digital in power ground
DESCRIPTION
ADC clock - 50Kohm internal pull-down resistor Video Sample clock - 50Kohm internal pull-down resistor Black Sample clock - 50Kohm internal pull-down resistor Line Clamp clock Input Enable - 50Kohm internal pull-down resistor Serial Port serial clock - 50Kohm internal pull-down resistor Serial Port Data I/O - 50Kohm internal pull-down resistor Serial Port Load - 50Kohm pull-down resistor Output driver VDD Output driver Ground ANALOG VDD RED ANALOG INPUT NEGATIVE RED ANALOG INPUT POSITIVE GREEN ANALOG INPUT NEGATIVE GREEN ANALOG INPUT POSITIVE BLUE ANALOG INPUT NEGATIVE BLUE ANALOG INPUT POSITIVE ANALOG GROUND External Bias Resistor -external 10Kohm resistor to ground ANALOG GROUND ANALOG VDD Common Mode Reference for ADC ADC Reference By-Pass ADC Reference By-Pass ANALOG VDD ANALOG GROUND ADC parallel out 7 ADC parallel out 6 ADC parallel out 5 ADC parallel out 4 Output driver VDD Output driver Ground ADC parallel out 3 ADC parallel out 2 ADC parallel out 2 ADC parallel out 1 (LSB) (MSB)
OFFSET AND GAIN PARALLEL IN 9 (MSB) OFFSET AND GAIN PARALLEL IN 8 OFFSET AND GAIN PARALLEL IN 7 OFFSET AND GAIN PARALLEL IN 6 OFFSET AND GAIN PARALLEL IN 5 OFFSET AND GAIN PARALLEL IN 4 OFFSET AND GAIN PARALLEL IN 3 OFFSET AND GAIN PARALLEL IN 2 OFFSET AND GAIN PARALLEL IN 1 OFFSET AND GAIN PARALLEL IN 0 (LSB) Digital VDD Digital Ground
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XRD9836
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16-BIT PIXEL GAIN AFE
REV. 1.0.0
ELECTRICAL CHARACTERISTICS - XRD9836 Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz, REXT=10K, Ta=25C
PARAMETER
SYMBOL
MIN.
TYP. A/D CONVERTER
MAX.
UNIT
CONDITIONS
Resolution Conversion Rate
R Fc3 Fc1
16 1.0 1.0 -0.024 0.002 40 15 +/-2 0.003 2 10 15 0.024
BITS MSPS MSPS % FS mV uV/C %FS %FS/C Vpp PER CHANNEL in 3-CH Mode PER CHANNEL in 1-CH Mode
Differential NonLinearity Input Referred Offset Offset Drift Input Referred Gain Error Gain Error Drift Input Voltage Range
DNL ZSE ZSD FSE FSD IVR
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
CONDITIONS
VOLTAGE REFERENCES Vref+ VrefVref Common Mode Delta Vref Vref(+) - Vref(-) CAPP CAPN VCMR VREF 1.475 0.425 0.970 0.85 1.7 0.7 1.15 1.00 1.925 0.875 1.430 1.15 V V V V
4
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XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
ELECTRICAL CHARACTERISTICS - XRD9836 (con't) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz, REXT=10K, Ta=25C
PARAMETER
SYMBOL
MIN.
TYP. CDS - S/H
MAX.
UNIT
CONDITIONS
Input Voltage Range
1.0 INVSR 0.5 1.2
V V V nA
CCD Mode, Gain = 1 to 10 CCD Mode, Gain = 2 to 20 CIS Mode, Gain = 0.5 to 5
Input Leakage Current Input Switch On Resistance
Iin
-40
8
40
Ron
50
150
At input pins: RED+/-, GRN+/-, BLU+/- when BSAMP is active guaranteed by design At input pins: RED+/-, GRN+/-, BLU+/- when BSAMP is inactive guaranteed by design CCD MODE
Input Switch Off Resistance Internal Voltage Clamp CDS Input (inverting) Internal Voltage Clamp S/H Input (Non-inverting)
Roff
100
MEG
Vclampccd
1.1
1.25
1.4
V
Vclampsh
-0.2
0.0
0.2
V
CIS MODE
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
CONDITIONS
OFFSET SPECIFICATIONS Fine Offset Range Fine Offset Step Dynamic Offset Range Dynamic Offset Step FOFRFOFR+ FOFRES DOFRDOFR+ DOFRES -125 120 -200 80 -128 +127 0.25 -80 +160 0.25 -55 250 -80 200 mV mV mV mV mV mV 10bit 10bit
5
XRD9836
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16-BIT PIXEL GAIN AFE
REV. 1.0.0
ELECTRICAL CHARACTERISTICS - XRD9836 (con't) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz, REXT=10K, Ta=25C
PARAMETER SYMBOL MIN. TYP. MAX. UNIT CONDITIONS
PGA SPECIFICATIONS Gain Range Min. (Absolute Value) Gain Range Max (Absolute Value) Gain Resolution GRAN MIN GRAN MAX GRES 0.8 1.8 7.8 16 1.0 2.05 9.2 18.5 0.008 0.016 MIN. TYP. MAX. 1.2 2.2 10.8 21 V/V V/V V/V Gain range = 1 to 10 Gain range = 2 to 20 Gain range = 1 to 10 Gain range = 2 to 20 Gain range = 1 to 10 Gain range = 2 to 20 CONDITIONS
PARAMETER
SYMBOL
UNIT
SYSTEM SPECIFICATIONS (INCLUDES CDS, PGA, AND A/D) Differential Non-Linearity Integral Non-Linearity Input Referred Noise PGA Gain=1 Input Referred Noise PGA Gain=20 DNL INL IRNmin -0.024 -2.4 0.002 +/- 0.1 1.7 +0.024 2.4 %FS %FS mVrms GAIN =1.5 GAIN = 1.5 GAIN = 1, inputs shorted together. GAIN = 20, inputs shorted together.
IRNmax
0.2
mVrms
6
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XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
ELECTRICAL CHARACTERISTICS - XRD9836 (con't) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz, REXT=10K, Ta=25C
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
CONDITIONS
CLOCK TIMING SPECIFICATIONS ADCLK Duty Cycle ADCLK period (1-Ch mode) ADCLK period (3-Ch mode) Single Channel Conversion period Three Channel Conversion period BSAMP Pulse Width VSAMP Pulse Width BSAMP sampling edge to VSAMP sampling edge Min. Time negedge ADCLK to sampling VSAMP VSAMP/BSAMP Acquisition time (aperture delay) Settling time Latency tadclk3 tadclk1 tcp1 tcp3 tcr1 tcr3 tpwb tpwv tbvf 49 49 66.6 33.3 66.6 100 20 20 50 51 51 % % ns ns ns ns ns ns ns 3-CH, Figure 17 & Figure 19 1-CH, Figure 18 & Figure 20 Figure 18 & Figure 20 Figure 17 & Figure 19 Figure 18 & Figure 20 Figure 17 & Figure 19 Figure 17 & Figure 19 Figure 17 & Figure 19 Figure 17 & Figure 19
tvfcr
12
ns
Figure 17 & Figure 19
tap
6
ns
Figure 17 & Figure 19
tstl tlat
15 9
ns cycles
Figure 17 & Figure 19 Figure 21 & Figure 22
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XRD9836
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16-BIT PIXEL GAIN AFE
REV. 1.0.0
ELECTRICAL CHARACTERISTICS - XRD9836 (con't) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz, REXT=10K, Ta=25C
PARAMETER SYMBOL MIN. TYP. MAX. UNIT CONDITIONS
USIO TIMING SPECIFICATIONS uSIO Data Setup Time uSIO Data Hold Time uSIO Load Setup Time uSIO Load Hold Time uSIO Period uSIO Data Valid Delay Tuss Tush Tusls Tuslh Tusp Tusdvd 10 10 10 10 40 0 ns ns ns ns ns Figure 15 & Figure 16 Figure 15 & Figure 16 Figure 15 & Figure 16 Figure 15 & Figure 16 Figure 15 & Figure 16 Figure 16
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/O TIMING SPECIFICATIONS OGI Enable time VSAMP to ADC setup time ADC to OGI data setup time ADC to OGI data hold time ADCLK to ADCDO data out delay LCLMP Pulse duration BSAMP/LCLMP setup BSAMP/LCLMP hold Tev Tva Togis Togih Tadcdo LCLMPd BLs BLh 8 4 4 4 4 4 1 1 50 ns pixels ns ns ns ns ns Figure 4 Figure 4
internal time adjustable
Figure 4
internal time adjustable
Figure 4
internal time adjustable
Figure 5
internal time adjustable more pixels preferred
8
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XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
ELECTRICAL CHARACTERISTICS - XRD9836 (con't) Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz, REXT=10K, Ta=25C
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
CONDITIONS
POWER SUPPLIES - 1 CHANNEL MODE Analog IDD Digital IDD Output IDD IDD Total Power Dissipation PARAMETER IAVDD IDVDD IOVDD IDD PDISS SYMBOL MIN. 47 5 5 57 188 TYP. MAX. mA mA mA mA mW UNIT Tested @ 3.6V Tested @ 3.6V Tested @ 3.6V Tested @ 3.6V Tested @ 3.6V CONDITIONS
POWER SUPPLIES - 3 CHANNEL MODE Analog IDD Digital IDD Output IDD IDD Total Power Dissipation Power Dissipation IAVDD IDVDD IOVDD IDD PDISS PDISS 60 1 1 62 220 84 9 11 104 343 280 110 15 15 140 500 mA mA mA mA mW mW Tested @ 3.6V Tested @ 3.6V Tested @ 3.6V Tested @ 3.6V Tested @ 3.6V Tested @ 3.0V
PARAMETER
SYMBOL
MIN.
TYP. DIGITAL I/O
MAX.
UNIT
CONDITIONS
Logic Input Low Logic Input High OGI Input Current High OGI Input Current Low Control Inputs Current High Control Inputs Current Low Logic Output Low Logic Output High Tristate Leakage
Vil Vih Iih Iil Iinh Iinl Vol Voh IOLeak VDD-0.5 -100 0.1 VDD-0.5 -100 -100 50 -5 90 0.1
0.5
V V
100 100 150 5 0.5
nA nA uA uA V V 50Kohm Pull down 50Kohm Pull down Isink=2.0mA Isrc=2.0ma
100
nA
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XRD9836
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16-BIT PIXEL GAIN AFE
REV. 1.0.0
SYSTEM OVERVIEW
The XRD9836 provides a 16-bit Analog Front End functionality for Mid-to-High range, next-generation scanner applications. It has 3 channels of Correlated Double Sampling (CDS), using a 10-bit Dynamic Offset DAC, a 10-bit Programmable Gain Amplifier (PGA) and a 10-bit Fine Offset DAC for Red, Green, and Blue CCD signals. A 16-bit 30MHz ADC is multiplexed among these 3 channels to provide digitized image data for the scanner ASIC chip. In 3-channel mode, the order of channels is R, G, B. In the 1-channel mode, only the selected channel is active. The XRD9836 provides one of the key requirements for the next generation scanner AFE's, the ability to control Pixel-by-Pixel Gain and Offset values. Figure 3 shows the ASIC and AFE interface for the proposed system. A 10-bit parallel bus Offset Gain Input Port (OGI) is used to transfer 10 bits of Gain and 10 bits of Offset. In the 3-channel mode, the data is received sequentially in the following order: red gain, red offset, green gain, green offset, blue gain, blue offset. In 1-channel mode, the data is received sequentially gain then offset. For an example of both 3-channel and 1-channel OGI timing see Figure 4. The Input Enable pin (IE) enables OGI port to program internal pixel gain and offset registers. If IE goes low, the gain and offset registers will store the last data while IE was high. For ADC outputs, the XRD9836 has an 8-bit parallel bus ADC Data Out (ADCDO). The ADC output data is transmitted sequentially in the following order for 3-ch mode red high order byte, red low order byte, green high order byte, green low order byte, blue high order byte, blue low order byte as shown in Figure 5 A three-pin, Micro-controller Serial I/O link (uSIO) is used to write or read from the XRD9836's internal configuration registers. The internal registers control the various modes of operation of the chip.
ADC OUT
8
O g n d GREEN HIGH ORDER ADC OUT GREEN LOW ORDER ADC OUT BLUE HIGH ORDER ADC OUT BLUE LOW ORDER ADC OUT RED HIGH ORDER ADC OUT RED LOW ORDER ADC OUT O v d d A g n d A v d d TIMING 10 Blue Offset Blue Gain BLUE CDS & PGA BLUE GAIN REGISTER BLUE OFFSET REGISTER SERIAL PORT 10 D v d d D g n d C M R E F R E X T BIAS 16-BIT 16 30MHZ ADC C A P P C A P N D E M U X B L U +
XRD9836 AFE
10
10
GREEN GAIN REGISTER GREEN OFFSET REGISTER
RED GAIN REGISTER RED OFFSET REGISTER
10
GREEN CDS & 10 Green Offset PGA
G R N +
RED CDS & PGA
G R N -
Green Gain
Red Offset
R E D -
Red Gain
R E D +
IE
ASIC
10
10
10
10
OFFSET GAIN INPUT
10
Green Offset
Green Gain
Blue Offset
Red Offset
Red Gain
Blue Gain
10
FIGURE 3. SYSTEM BLOCK DIAGRAM
10
ADCLK (30MHz)
DSP
ADCLK
10
SCLK SDATA LOAD
VSAMP BSAMP LCLMP
B L U -
M U X
3
3
2
2
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GAIN SELECT:
The XRD9836's Gain range is selectable to either 1 to 10 or 2 to 20 with the Gain Select Bit. If Gain of 1 to 10 is selected (Gain Select bit = 0), the maximum input is 1.0V. If Gain of 2 to 20 is selected (Gain Select bit = 1), the maximum input is 0.5V.
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
also reminded that data coming out of the ADC outputs will have latency from the gain and offset provided (10 ADC cycles for single color and 12 cycles for 3-color). This latency includes the cycles to put the gain and offset data into the registers and the latency of the ADC itself (9 ADCLK cycles). Sampling of the OGI parallel input port is defined as the red gain data being the first pulse of ADCLK after VSAMP, therefor VSAMP must occur before a rising edge of ADCLK. It is also recommended that VSAMP__OGI_DLY (DelayD[7:4]) should be smaller than OGI_DLY (DelayA[7:4]) to make sure the correct data is sampled, and that relationship is not reversed internally.
PARALLEL PORT FOR PIXEL OFFSET AND GAIN CONTROL (OGI):
The timing diagram in Figure 4 shows the Offset and Gain Inputs (OGI) and ADCLK in relationship to VSAMP.
3 - Channel OGI Timing
Tev IE Tva VSAMP ADCLK OGI 10-bit parallel input Togis RG RO Togih GG GO BG BO RG
PARALLEL PORT FOR ADC OUTPUT (ADCDO):
The timing diagram, Figure 5, shows the ADC output (ADCDO). The XRD9836 will be clocking ADC high order bytes on the rising edge of ADCLK and clocking ADC low order bytes on the falling edge of ADCLK. As noted the RGB data is synchronized to sampling edge of VSAMP.
1 - Channel OGI Timing
Tev IE Tva VSAMP
3 - Channel ADCDO Timing
ADCLK OGI 10-bit parallel input
VSAMP
Gain Togis Offset Togih Gain
ADCLK ADCDO 8-bit parallel output BDL RDH RDL GDH GDL BDH BDL
FIGURE 4. OGI TIMING (ADCLKPOL=0, VSAMPPOL=0) The ASIC chip will be clocking OGI data at six times the pixel rate clock in 3-CH mode and two times the pixel rate in 1-CH mode. The gain data is grabbed on the rising edge of ADCLK and the offset data on the falling edge of ADCLK. The OGI port is read into internal pixel gain and offset registers only when Input Enable (IE) is active before the sampling edge of VSAMP as shown above. As noted the RGB gain/offset data is synchronized to sampling edge of VSAMP. Note that ADCLK frequency is 3X the pixel rate in 3CH mode and 1X the pixel rate in 1-CH mode. The ADCLK's duty cycle is required to be 50%. It is assumed that the OGI port and ADCLK input have matched output drivers inside the ASIC, matched trace lengths on the PCB between the ASIC and the XRD9836, and matched delays at input buffers inside the XRD9836 in order to receive OGI data on both edges of ADCLK error free. The latency between the input of the parallel inputs and their effective application is 1 pixel. The user is
Tadcdo
1 - Channel ADCDO Timing
VSAMP ADCLK ADCDO 8-bit parallel output DH Tadcdo DL
FIGURE 5. ADCDO TIMING (ADCLKPOL=0, VSAMPPOL=0)
PIXEL GAIN/OFFSET CONTROL (FGOM OR PGOM):
Figure 6 shows the block diagram of the CDS/PGA/ Offset DACs/ADC signal path. The offset for each channel is controlled by a 10-bit Dynamic offset DAC before the CDS amplifier and a 10-bit Fine offset DAC after the PGA amplifier. Thus, the total offset of each channel is controlled by two 10-bit offset DACs. The Dynamic offset DAC will have a range of -80mV to +160mV, with the ability to adjust the CDS stage offset to within +/- 0.25mV. The Fine offset DAC will 11
XRD9836
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16-BIT PIXEL GAIN AFE
REV. 1.0.0
have a range of +/- 128mV, with the ability to adjust PGA offsets to within +/- 0.25mV. There are two modes of operation for Pixel Gain and Offset control. The first is a fixed gain and offset control mode where the gain and offset is adjusted once per line or per scan. The second mode is a pixel to pixel adjustment of gain and offset. This mode allows for gain and offset adjustment for each and every pixel. These modes are controlled by bit D0, GOM (Gain Offset Mode), in the MODE register. In FGOM (Fixed Gain/Offset Mode, GOM=0), the user can program the PGA gain, Dynamic and Fine Offset registers through the micro-controller serial interface (uSIO). In PPGOM (pixel-by-pixel gain and offset mode, GOM=1), the user can input 10 bits of Gain and 10 bits of Dynamic offset data through the OGI port.
OB Pixels VBlack VDark Active Pixels V Black
CCD Waveform
VVideo
FIGURE 7. CCD WAVEFORM - DEFINITION OF TERMS
CCD OUTPUT INFORMATION = (VBLACK-VVIDEO)
LCLMP TIMING:
In order to reject higher frequency power supply noise which is not attenuated near the sampling frequency, the XRD9836 utilizes a fully differential input structure. Since the CDS process uses AC coupled inputs, the coupling capacitor must be charged to the common-mode range of the analog front-end. This can be accomplished by clamping the coupling capacitor to the internal clamp voltage when the CCD is at a reference level at the beginning of each line using LCLMP. This needs to be done for enough clamping time (Tclamp) which is determined by external Capacitor, internal switch resistance, BSAMP pulse width and number of samples during line clamp. The maximum capacitance is
N * tp w b ( Rc + R s ) * ln
NC
CDS Signal
CDS
+
PGA 10 Bit
+ 3:1 MUX ADC
Dynamic Offset DAC 10 BIT
Fine Offset DAC 10 BIT
FIGURE 6. CDS TO ADC SIGNAL PATH
CCD MODE(CORRELATED DOUBLE SAMPLING):
Correlated double sampling is a technique used to level shift and acquire CCD output signals whose information is equal to the difference between consecutive reference (VBlack) and signal (VVideo) samples. The CDS process consists of three steps: 1) Sampling and holding the reference black level (VBlack). 2) Sampling the video level (VVideo). 3) Subtracting the two samples to extract the video information. (CCD signal information = VBlack- VVideo) Once the CCD signal information has been extracted, it can be processed further through amplification and/ or offset adjustment. Since system noise is also stored and subtracted during the CDS process, signals with bandwidths less than half the sampling frequency will be substantially attenuated. where
CM A X =
( V rV-eV c)
tpwb = clamp pulse width (BSAMP typ 25ns) N = number of pixels used for clamping Rc = clamp resistance (typ 50ohms) Rs = signal source resistance (typ 50ohms) Vr = black level Vc = clamp voltage (1.2V) Ve = error voltage (3.05uV worst case)
The clamp LCLMP should be active for at least 4 pixels during Optical Black (OB) and should be inactive during all of the Active portion of the line. Usually OB lasts for 40 - 50 pixels. It is better if LCLMP remains active during as much of OB as possible. LCLMP should be set Active 1ns before BSAMP leading edge and should be held for at least 1ns after BSAMP trailing edge.
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In addition to the above requirement for LCLMP on a line by line basis there is an additional requirement for a one time LCLMP upon power-up to provide the AC coupling capacitor's initial charge. The one time LCLMP pulse width can also be determined from the Cmax equation above. A typical value, using 1 nf cap, with initial charge of 3V (Vr - Vc), and a BSAMP pulse width of 25ns, is estimated to be 1.4us. This is equivalent to one time LCLMP of 56 OB pixels upon power up.
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
4. VSAMP should have typ > 25ns pulse width. 5. LCLMP is not needed for CIS Applications. (except for APOAM even and odd selection) 6. Input Voltage Range: Vcm @ Vin- = 0 to 1.4 V CIS Signal @ Vin+ = 0 to 1.2 V above Vcm offset
3-CHANNEL CDS MODE:
This mode allows simultaneous CDS of the red, green and blue inputs. Black-level sampling occurs on each pixel and is equal to the width of the BSAMP sampling input. The black level is held on the sampling edge of BSAMP and the PGA will immediately begin to track the signal input until the sampling edge of VSAMP. At the end of the video sampling phase, the difference between the reference and video levels is inverted, amplified, and offset depending on the contents of the PGA gain and offset registers. The RGB channels are then sequentially converted by a high-speed A/D converter. Converted data appears on the data output bus after 9 ADCLK cycles. The red channel is synchronized on the rising edge of the first ADCLK after the sampling edge of VSAMP. The power-up default mode is for CDS sampling a CCD input.
CIS Signal Vcm (DCoffset) 3:1 MUX ADC
NC
CDS
+
PGA 10 bit
+
Dynamic Offset DAC 10 bit
Fine Offset DAC 10 bit
FIGURE 8. CIS SIGNAL PATH
Pixel N-1
Pixel N
Pixel N+1
Pixel N+2
Pixel N+3
C IS
W avef m or
Vcm
INVSR
1-CHANNEL CDS MODE:
The 1-Channel CDS mode allows high-speed acquisition and processing of a single channel. The timing, clamp and buffer configurations are similar to the 3channel mode described previously. To select a single channel input, the color bits of configuration selected by CHAN[1:0] bits, in the MODE register, must be set to the appropriate value. The A/D input will begin to track the selected color input on the next positive edge of ADCLK. If the configuration is toggled from a single color mode to 3-channel mode, RGB scanning will not occur until the circuit is re-synchronized on the sampling edge of VSAMP.
FIGURE 9. CIS WAVEFORM -DEFINITION OF TERMS
3-CHANNEL CIS AND S/H MODE
The XRD9836 also supports operation for Contact Image Sensor (CIS) and S/H applications. The red channel is synchronized on the rising edge of the first ADCLK after the sampling edge of VSAMP. In this mode of operation, the BSAMP input is connected to DGND, and input sampling occurs on the falling edge of VSAMP(VSAMP_POL=0).
1-CHANNEL CIS AND S/H MODE:
The 1-channel CIS S/H mode allows high-speed acquisition and processing of a single channel. The timing, clamp and buffer configurations are similar to the 3-channel mode. In single channel mode one color channel is selected using CHAN[1:0]. If the configuration is toggled from single color to 3-channel mode, RGB scanning will not occur until the circuit is re-synchronized by the first sampling edge of VSAMP.
CIS MODE:
The AFE can be configured for inputs from a CCD or a CIS type device by setting the CCD_CIS bit. For CIS mode, the following interface features are provided: 1. DC Coupled Inputs. 2. Gain Range is 0.5 to 5 with 10 bit resolution. 3. It is assumed that CIS Sample and Hold Outputs and DC offset buffer have low output impedances(~50 ohms). 13
XRD9836
xr
XRD9836 has included a programmable delay function to help simplify this job. There are four serial interface registers, DelayA, DelayB, DelayC and DelayD, used to program various delays of the pixel timing and Data and OGI bus timing. Each register is divided into 2 delay parameters. Each delay parameter is 4 bits wide. DelayA[7:4] controls the OGI sampling delay. These bits program the delay of the ADCLK used to sample the OGI input bus. Delay is added in 1ns increments. See Figure 12. DelayA[3:0] controls the ADCDO delay. These bits are used to program the timing delay added to the ADCDO data bus updates. Delay is added in 1ns increments. See Figure 11. DelayB[7:4] controls the amount of delay added to the leading edge of BSAMP. Delay to the leading edge will be added in 0.5ns increments. This can help to position the leading edge of the internal BSAMP away from the reset pulse of the CCD input. See Figure 11. DelayB[3:0] controls the amount of delay added to the trailing edge of BSAMP. Delay to the trailing edge will be added in 0.5ns increments. This will allow for adjustment of the Black Level sampling position by the internal BSAMP. See Figure 11. DelayC[7:4] controls the amount of delay added to the leading edge of VSAMP. Delay will be added in 0.5ns increments. This can help to position the leading edge of the internal VSAMP to track the video portion of the CCD input. See Figure 11. DelayC[3:0] controls the amount of delay added to the trailing edge of VSAMP. Delay will be added in 0.5ns increments. This will allow for adjustment of the Video Level sampling position by the internal VSAMP. See Figure 11. DelayD[7:4] controls the amount of delay added to the VSAMP OGI. The internal VSAMP_OGI is used to transfer the input OGI register data to the PGA and OFFSET control. Delay is added in 1ns increments. Please note the falling edge of the internal VSAMP_OGI must occur before the rising edge of the OGI sampling clock. See Figure 12. DelayD[3:0] controls the amount of delay added to the ADCLK. Delay is added to the internal ADCLK in 0.5ns increments. See Figure 11.
16-BIT PIXEL GAIN AFE
REV. 1.0.0
TIMING - CLOCK BASICS:
The XRD9836 has 4 clock signals BSAMP, VSAMP, ADCLK and LCLMP. These inputs control the sampling, clamping and synchronization functions of the device. The pixel rate clocks are BSAMP, VSAMP and ADCLK. BSAMP controls the sampling of the black reference level of a CCD input signal. VSAMP controls the sampling of the video level of a CCD or CIS output signal. The ADCLK controls the internal sampling of the PGA by the ADC and ADC operation. The line rate clock, LCLMP, performs the clamping and synchronization functions. The clamp function sets the bias point for the external AC coupling capacitor on the inputs. Synchronization defines the odd pixel in the APOAM mode. CLOCK POLARITY Each of the 4 timing signals has a separate polarity control bit in the CONTROL register. Figure 10 shows the logic implementation of the polarity control. If the polarity bit is low (default) BSAMP and VSAMP sample on the falling edge, LCLMP is active high and ADCLK must be low during the VSAMP falling edge. See timing examples if Figure 17 and Figure 18 If any of the external timing signals are inverted from the default timing simply write a "1" to the appropriate polarity bit to compensate.
BSAMP VSAMP ADCLK
Polarity Polarity Polarity Delays Clock Logic AFE ADC OGI
LCLMP
Polarity
FIGURE 10. CLOCK POLARITY AND DELAYS DELAY CONTROL One of the more difficult tasks in designing a scanner is optimizing the pixel and interface (data output & OGI) timing for a CCD, CDS and ADC. The
14
xr
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
tPIX Black Sample Point CCD Signal tBK tVD DelayB[7:4] BSAMP DelayB[3:0] internal BSAMP Video Sample Point
VSAMP DelayC[3:0] internal VSAMP DelayC[7:4]
ADCLK DelayD[3:0] internal ADCLK DelayD[3:0]
ADCDO Output Bus
Tadcdo DelayA[3:0]
FIGURE 11. PIXEL TIMING & ADCDO (OUTPUT DATA) DELAY ADJUSTMENT
Pixel (n-1)
tPIX Black Sample Point CCD Signal Video Sample Point
Pixel (n)
OGI Input Bus
Gain (n)
Offset (n)
Togis Togih
Gain (n+1)
OGI Gain Sample Point
Offset (n+1)
OGI Offset Sample Point
VSAMP DelayD[7:4] internal OGI VSAMP DelayD[7:4]
ADCLK DelayA[7:4] internal OGI sample delay DelayA[7:4]
FIGURE 12. OGI TIMING DELAY ADJUSTMENT
15
XRD9836
xr
In the PPGOM mode, the APOAM can be selected only when Input Enable (IE) is disabled. The last dynamic gain and offset programmed using the OGI port are used for the odd pixels. The APOAM dynamic offset and the APOAM fine register values, programmed through the USIO port are used for the even pixels. The gain value is fixed as the last received value through the serial port. This is shown in Figure 14.
16-BIT PIXEL GAIN AFE
REV. 1.0.0
ALTERNATE PIXEL OFFSET ADJUST MODE (APOAM):
In some applications, alternate pixels along a scan line come from two different rows of CCD's, causing a systematic offset between alternate pixels. When the XRD9836 is operated in the Fixed Gain Offset Mode (FGOM), it does not have the ability to compensate for this alternating offset phenomenon. To compensate for these offsets, this chip has an Alternate Pixel Offset Adjust mode (APOAM), which can be enabled by writing a 1 to the APOAM bit (D1of the MODE register) through the serial port. In APOAM mode each channel has four 10-bit offset registers to control offset. Odd pixel offsets are compensated for by the Dynamic Offset Register value and the Fine Offset Register value. The even pixel offsets are compensated for by the APOAM Dynamic Offset Register value and the APOAM Fine Offset Register value. The individual channel pixel gains do not change and are determined by the red, green and blue PGA gain register settings.
SUMMARY OF APOAM USABILITY:
MODE
FIXED GAIN/OFFSET FIXED GAIN/OFFSET PIXEL GAIN/OFFSET PIXEL GAIN/OFFSET
IE
OFF ON OFF ON
APOAM
USABLE USABLE USABLE NOT USABLE
TABLE 1: SUMMARY OF APOAM USABILITY
NC 3:1 MUX +
CDS Signal
CDS
+
PGA 10 Bit
ADC
LCLMP VSAMP
Dynamic Offset DAC 10 BIT
Fine Offset DAC 10 BIT
Dyn. Reg. APOAM Dyn. Reg.
Fine Reg. APOAM Fine Reg.
DYNAMIC OFFSET FINE OFFSET
ODD ODD
EVEN EVEN
ODD ODD
EVEN EVEN
FIGURE 13. APOAM MODE - CONFIGURATION OF OFFSET REGISTERS The offset alternates every other pixel. The first pixel and all odd pixels in the line use the dynamic offset and fine offset register values. The even pixels use the APOAM dynamic offset and the APOAM fine offset register values. Odd pixels are defined from the first ADCLK after the fall of LCLMP.
Figure 14. APOAM SYNCHRONIZATION AND REGISTER ALTERNATION Note: LCLMP also defines which pixel is even or odd. The first pixel after LCLMP goes inactive is odd. Position LCLMP so that there are an even number of pixels before start of active pixels.
16
xr
MICRO-CONTROLLER SERIAL PORT FOR MODE CONTROL (USIO):
The uSIO is a bidirectional I/O port which is used for configuring various operating modes as well as phase aligning internal clocks (delay control). The serial port can be used to program any of the registers listed in the registers table. Note that SDIO is a bidirectional pin used to read or write the XRD9836 internal registers. The R/W bit will define the direction of the bus after Address bits. If R/W = 0, a write to the XRD9836 is performed. If R/W = 1, a read of the XRD9836's internal registers is performed. During a write operation there must be 18 positive edges of SCLK between the fall of LOAD and the rise of LOAD. If there are more or less than 18, the write operation will not take place. For a write to the
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
XRD9836 the SDIO pin stays configured as an input for entire 18 SCLK's before LOAD goes high. The E0 and E1 bits are dummy (unused) bits. For a read of the XRD9836 internal registers (R/W=1) the E0 and E1 are used as a transition time for the SDIO pin going from an input to a output. During this time SDIO pin is tri-stated. SDIO is an input while serial port accepts the address of the register to be read and during the E0 and E1 time period transitions to an output for the read operation. During a read operation the first 18 positive edges are used. If there are less than 18, not all of the data will be output. If there are more than 18, only the first 18 bits will be valid. The data becomes valid after the rising edge of SCLK.
Tusls Tuss
LOAD SCLK
msb lsb A3 A2 A1 A0 E1 E0 msb D9 D8 D7 D6 D5
Tusp Tush
Tuslh
lsb D4 D3 D2 D1 D0
SDIO
R/W
A4
Write
Register Address
Dummy bits
Write Register Data
SDIO configured as
Input
FIGURE 15. SERIAL PORT WRITE TIMING (R/W=0)
Tusls Tuss
LOAD SCLK
msb lsb A3 A2 A1 A0
Tusp Tush
Tuslh Tusdvd
msb E1 E0 D9 D8 D7 D6 D5 D4 D3 D2 D1
lsb D0
SDIO
R/W
A4
Read
Register Address
Dummy bits
Read Register Data
SDIO configured as
Input
Tri-state
Output
FIGURE 16. SERIAL PORT READ TIMING (R/W=1) 17
XRD9836
xr
16-BIT PIXEL GAIN AFE
REV. 1.0.0
REGISTERS
ADDRESS
A 4 0 0 0 0 0 A 3 0 0 0 0 0 A 2 0 0 0 0 1 A 1 0 0 1 1 0 A 0 0 1 0 1 0
DATA BITS D9
RPGA [9] GPGA [9] BPGA [9] RDOFF [9] GDOFF [9] BDOFF [9] RFOFF [9] GFOFF [9] BFOFF [9] ARDOF [9] AGDOF [9] ABDOF [9] ARFOF [9] AGFOF [9] ABFOF [9]
D8
RPGA [8] GPGA [8] BPGA [8] RDOFF [8] GDOFF [8] BDOFF [8] RF0FF [8] GF0FF [8] BF0FF [8] ARDOF [8] AGDOF [8] ABDOF [8] ARFOF [8] AGFOF [8] ABFOF [8]
D7
RPGA [7] GPGA [7] BPGA [7] RDOFF [7] GDOFF [7] BDOFF [7] RFOFF [7] GFOFF [7] BFOFF [7] ARDOF [7] AGDOF [7] ABDOF [7] ARFOF [7] AGFOF [7] ABFOF [7] ADC POL DelayA [7] DelayB [7] DelayC [7] DelayD [7] NOFS2
D6
RPGA [6] GPGA [6] BPGA [6] RDOFF [6] GDOFF [6] BDOFF [6] RF0FF [6] GF0FF [6] BF0FF [6] ARDOF [6] AGDOF [6] ABDOF [6] ARFOF [6] AGFOF [6] ABFOF [6] LCLMP POL DelayA [6] DelayB [6] DelayC [6] DelayD [6] TEST ENABLE do not change
D5
RPGA [5] GPGA [5] BPGA [5] RDOFF [5] GDOFF [5] BDOFF [5] RFOFF [5] GFOFF [5] BFOFF [5] ARDOF [5] AGDOF [5] ABDOF [5] ARFOF [5] AGFOF [5] ABFOF [5] BSAMP POL DelayA [5] DelayB [5] DelayC [5] DelayD [5] GAIN SELECT do not change
D4
RPGA [4] GPGA [4] BPGA [4] RDOFF [4] GDOFF [4] BDOFF [4] RFOFF [4] GFOFF [4] BFOFF [4] ARDOF [4] AGDOF [4] ABDOF [4] ARFOF [4] AGFOF [4] ABFOF [4] VSAMP POL DelayA [4] DelayB [4] DelayC [4] DelayD [4] CCD/CIS do not change
D3
RPGA [3] GPGA [3] BPGA [3] RDOFF [3] GDOFF [3] BDOFF [3] RFOFF [3] GFOFF [3] BFOFF [3] ARDOF [3] AGDOF [3] ABDOF [3] ARFOF [3] AGFOF [3] ABFOF [3] DLP Disable DelayA [3] DelayB [3] DelayC [3] DelayD [3] CHAN [1] do not change
D2
RPGA [2] GPGA [2] BPGA [2] RDOFF [2] GDOFF [2] BDOFF [2] RFOFF [2] GFOFF [2] BFOFF [2] ARDOF [2] AGDOF [2] ABDOF [2] ARFOF [2] AGFOF [2] ABFOF [2] PwrDwn DelayA [2] DelayB [2] DelayC [2] DelayD [2] CHAN [0] do not change
D1
RPGA [1] GPGA [1] BPGA [1] RDOFF [1] GDOFF [1] BDOFF [1] RFOFF [1] GFOFF [1] BFOFF [1] ARDOF [1] AGDOF [1] ABDOF [1] ARFOF [1] AGFOF [1] ABFOF [1] OEB DelayA [1] DelayB [1] DelayC [1] DelayD [1] APOAM do not change
D0
RPGA [0] GPGA [0] BPGA [0] RDOFF [0] GDOFF [0] BDOFF [0] RFOFF [0] GFOFF [0] BFOFF [0] ARDOF [0] AGDOF [0] ABDOF [0] ARFOF [0] AGFOF [0] ABFOF [0] RESET DelayA [0] DelayB [0] DelayC [0] DelayD [0] GOM do not change
RED PGA GREEN PGA BLUE PGA RED DYNAMIC OFFSET GREEN DYNAMIC OFFSET BLUE DYNAMIC OFFSET RED FINE OFFSET GREEN FINE OFFSET BLUE FINE OFFSET APOAM RED DYNAMIC OFFSET APOAM GREEN DYNAMIC OFFSET APOAM BLUE DYNAMIC OFFSET APOAM RED FINE OFFSET APOAM GREEN FINE OFFSET APOAM BLUE FINE OFFSET CNTRL/POL DELAY A DELAY B DELAY C DELAY D MODE TEST
0 0 0 0 0
0 0 0 1 1
1 1 1 0 0
0 1 1 0 0
1 0 1 0 1
0
1
0
1
0
0
1
0
1
1
0 0 0 0 1 1 1 1 1 1
1 1 1 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 1 1
0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1
do not change
do not change
do not change
Table 2:
NOTE: Note: Shaded cells represent unused bits
18
xr
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
Red PGA Register
RPGA (00000) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RPGA [9]
RPGA [8]
RPGA [7]
RPGA [6]
RPGA [5]
RPGA [4]
RPGA [3]
RPGA [2]
RPGA [1]
RPGA [0]
0
0
0
0
0
0
0
0
0
0
RPGA[9:0] is used to set the gain of the Programmable Gain Amplifier (PGA) for the red channel. Code = 0000000000 is minimum gain. Code = 1111111111 is maximum gain.
Green PGA Register
GPGA (00001) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GPGA [9]
GPGA [8]
GPGA [7]
GPGA [6]
GPGA [5]
GPGA [4]
GPGA [3]
GPGA [2]
GPGA [1]
GPGA [0]
0
0
0
0
0
0
0
0
0
0
GPGA[9:0] is used to set the gain of the Programmable Gain Amplifier (PGA) for the green channel. Code = 0000000000 is minimum gain. Code = 1111111111 is maximum gain.
Blue PGA Register
BPGA (00010) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BPGA [9]
BPGA [8]
BPGA [7]
BPGA [6]
BPGA [5]
BPGA [4]
BPGA [3]
BPGA [2]
BPGA [1]
BPGA [0]
0
0
0
0
0
0
0
0
0
0
BPGA[9:0] sets the gain of the Programmable Gain Amplifier (PGA) for the blue channel. Code = 0000000000 is minimum gain. Code = 1111111111 is maximum gain.
Red Dynamic Offset Register
RDOFF (00011) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RDOFF [9]
RDOFF [8]
RDOFF [7]
RDOFF [6]
RDOFF [5]
RDOFF [4]
RDOFF [3]
RDOFF [2]
RDOFF [1]
RDOFF [0]
0
1
0
1
0
1
0
1
0
1
RDOFF[9:0] sets the course offset level prior to the PGA of the Red channel. Code = 0000000000 is -80mV. Code =1111111111 is +160mV. Default is Code 0101010101 = 0 mV.
19
XRD9836
xr
16-BIT PIXEL GAIN AFE
REV. 1.0.0
Green Dynamic Offset Register
GDOFF (00100) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GDOFF [9]
GDOFF [8]
GDOFF [7]
GDOFF [6]
GDOFF [5]
GDOFF [4]
GDOFF [3]
GDOFF [2]
GDOFF [1]
GDOFF [0]
0
1
0
1
0
1
0
1
0
1
GDOFF[9:0] sets the course offset level prior to the PGA of the Green channel. Code = 0000000000 is -80mV. Code =1111111111 is +160mV. Default is Code 0101010101 = 0 mV.
Blue Dynamic Offset Register
BDOFF (00101) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BDOFF [9]
BDOFF [8]
BDOFF [7]
BDOFF [6]
BDOFF [5]
BDOFF [4]
BDOFF [3]
BDOFF [2]
BDOFF [1]
BDOFF [0]
0
1
0
1
0
1
0
1
0
1
BDOFF[9:0] sets the course offset level prior to the PGA of the Blue channel. Code = 0000000000 is -80mV. Code =1111111111 is +160mV. Default is Code 0101010101 = 0 mV.
Red Fine Offset Register
RFOFF (00110) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RFOFF [9]
RF0FF [8]
RFOFF [7]
RF0FF [6]
RFOFF [5]
RFOFF [4]
RFOFF [3]
RFOFF [2]
RFOFF [1]
RFOFF [0]
1
0
0
0
0
0
0
0
0
0
RFOFF[9:0] sets the fine offset level after the PGA in the Red channel. Code = 0000000000 is -128mV. Code =1111111111 is +128mV. Default is Code 1000000000 = 0 mV.
Green Fine Offset Register
GFOFF (00111) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GFOFF [9]
GFOFF [8]
GFOFF [7]
GFOFF [6]
GFOFF [5]
GFOFF [4]
GFOFF [3]
GFOFF [2]
GFOFF [1]
GFOFF [0]
1
0
0
0
0
0
0
0
0
0
GFOFF[9:0] sets the fine offset level after the PGA in the Green channel. Code = 0000000000 is -128mV. Code =1111111111 is +128mV. Default is Code 1000000000 = 0 mV.
20
xr
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
Blue Fine Offset Register
BFOFF (01000) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BF0FF [9]
BFOFF [8]
BFOFF [7]
BF0FF [6]
BFOFF [5]
BFOFF [4]
BFOFF [3]
BFOFF [2]
BFOFF [1]
BFOFF [0]
1
0
0
0
0
0
0
0
0
0
BFOFF[9:0] sets the fine offset level after the PGA in the Blue channel. Code = 0000000000 is -128mV. Code =1111111111 is +128mV. Default is Code 1000000000 = 0 mV.
APOAM Red Dynamic Offset Register
ARDOF (01001) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ARDOF [9]
ARDOF [8]
ARDOF [7]
ARDOF [6]
ARDOF [5]
ARDOF [4]
ARDOF [3]
ARDOF [2]
ARDOF [1]
ARDOF [0]
0
1
0
1
0
1
0
1
0
1
RDOFF[9:0] sets the course offset level prior to the PGA of the Red channel for even pixels in APOAM Mode. Code = 0000000000 is -80mV. Code =1111111111 is +160mV. Default is Code 0101010101 = 0 mV.
APOAM Green Dynamic Offset Register
AGDOF (01010) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AGDOF [9]
AGDOF [8]
AGDOF [7]
AGDOF [6]
AGDOF [5]
AGDOF [4]
AGDOF [3]
AGDOF [2]
AGDOF [1]
AGDOF [0]
0
1
0
1
0
1
0
1
0
1
GDOFF[9:0] sets the course offset level prior to the PGA of the Green channel for even pixels in APOAM Mode. Code = 0000000000 is -80mV. Code =1111111111 is +160mV. Default is Code 0101010101 = 0 mV.
APOAM Blue Dynamic Offset Register
ABDOF (01011) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ABDOF [9]
ABDOF [8]
ABDOF [7]
ABDOF [6]
ABDOF [5]
ABDOF [4]
ABDOF [3]
ABDOF [2]
ABDOF [1]
ABDOF [0]
0
1
0
1
0
1
0
1
0
1
BDOFF[9:0] sets the course offset level prior to the PGA of the Blue channel for even pixels in APOAM Mode. Code = 0000000000 is -80mV. Code =1111111111 is +160mV. Default is Code 0101010101 = 0 mV.
21
XRD9836
xr
16-BIT PIXEL GAIN AFE
REV. 1.0.0
APOAM Red Fine Offset Register
ARFOF (01100) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ARFOF [9]
ARFOF [8]
ARFOF [7]
ARFOF [6]
ARFOF [5]
ARFOF [4]
ARFOF [3]
ARFOF [2]
ARFOF [1]
ARFOF [0]
1
0
0
0
0
0
0
0
0
0
RFOFF[9:0] sets the fine offset level after the PGA of the Red channel for even pixels in APOAM Mode. The offset is adjusted in 1mV increments. Code = 0000000000 is -128mV. Code =1111111111 is +128mV. Default is Code 1000000000 = 0 mV.
APOAM Green Fine Offset Register
AGFOF (01101) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AGFOF [9]
AGFOF [8]
AGFOF [7]
AGFOF [6]
AGFOF [5]
AGFOF [4]
AGFOF [3]
AGFOF [2]
AGFOF [1]
AGFOF [0]
1
0
0
0
0
0
0
0
0
0
GFOFF[9:0] sets the fine offset level after the PGA of the Green channel for even pixels in APOAM Mode. The offset is adjusted in 1mV increments. Code = 0000000000 is -128mV. Code =1111111111 is +128mV. Default is Code 1000000000 = 0 mV.
APOAM Blue Fine Offset Register
ABFOF (01110) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ABFOF [9]
ABFOF [8]
ABFOF [7]
ABFOF [6]
ABFOF [5]
ABFOF [4]
ABFOF [3]
ABFOF [2]
ABFOF [1]
ABFOF [0]
1
0
0
0
0
0
0
0
0
0
BFOFF[9:0] sets the fine offset level after the PGA of the Blue channel for even pixels in APOAM Mode. The offset is adjusted in 1mV increments. Code = 0000000000 is -128mV. Code =1111111111 is +128mV. Default is Code 1000000000 = 0 mV.
22
xr
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
Control / Polarity Register
CNTRL / POL (01111) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ADC POL
LCLMP POL
BSAMP POL
VSAMP POL
DLP DISABLE
PWRDWN
OEB
RESET
0
0
0
0
0
0
0
0
The CNTRL / POL register is used to program various options including: input timing polarity control, dynamic low power disable, power down for the chip, output enable, and reset. Reset will reset ALL registers including reset. All the clock inputs (except the serial interface SCLK) can be programmed to be active high or active low. See the "Timing" section for more information. ADCpol, LCLMPpol, BSAMPpol, and VSAMPpol set the polarity of ADCLK, LCLMP, BSAMP, and VSAMP respectively. ADCpol - Sets the polarity of the ADCLK input. ADCpol = 0, ADCLK low during VSAMP. ADCpol = 0, ADCLK inverted so that it is high during VSAMP. LCLMPpol - Sets the polarity of the LCLMP input. LCLMPpol = 0, LCMLP is active high during clamping operation and odd pixel determined from falling edge. BSAMPpol - Sets the polarity of the BSAMP input. BSAMPpol = 0, BSAMP is active high. The CCD black level is sample by the falling edge. BSAMPpol = 1, BSAMP is active low. The CCD black level is sample by the rising edge. VSAMPpol - Sets the polarity of the VSAMP input. VSAMPpol = 0, VSAMP is active high. The CCD video level is sample by the falling edge. VSAMPpol = 1, VSAMP is active low. The CCD video level is sample by the rising edge. DLP DISABLE (ADC Dynamic Low Power Disable) PWRDWN - Puts the XRD9836 into power down state. PWRDWN = 0, normal operation. PWRDWN = 1, low power state. OEB - Enables the ADCDO bus. OEB = 0, data valid on ADCDO bus. OEB = 1, ADCDO bus high impedance. RESET - Will reset the XRD9836 to default (power up) conditions. RESET = 0, normal operation. RESET = 1, all internal registers set to default values and clears itself after ~ 10ns.
23
XRD9836
xr
16-BIT PIXEL GAIN AFE
REV. 1.0.0
Delay Registers
DelayA (10000)
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DelayA [7] 1 DelayB [7] 0 DelayC [7] 0 DelayD [7] 0
DelayA [6] 0 DelayB [6] 0 DelayC [6] 0 DelayD [6] 0
DelayA [5] 0 DelayB [5] 0 DelayC [5] 0 DelayD [5] 0
DelayA [4] 0 DelayB [4] 0 DelayC [4] 0 DelayD [4] 0
DelayA [3] 0 DelayB [3] 0 DelayC [3] 0 DelayD [3] 0
DelayA [2] 0 DelayB [2] 0 DelayC [2] 0 DelayD [2] 0
DelayA [1] 0 DelayB [1] 0 DelayC [1] 0 DelayD [1] 0
DelayA [0] 0 DelayB [0] 0 DelayC [0] 0 DelayD [0] 0
default
DelayB (10001)
default
DelayC (10010)
default
DelayD (10011)
default
DelayA[7:4] - Controls the OGI_DLY. These bits are used to program the timing delay of the ADCLK used to sample the Offset-Gain-Inputs (OGI). Code 0000 is delay of 0ns, and code 1111 is 15ns. Default is 1000 = 7 ns. OGI_DLY should be larger than VSAMP_OGI_DLY. DelayA[3:0] - Controls the ADCO_DLY. These bits are used to program the timing delay of ADCO outputs in relation to ADCLK. Code 0000 is delay of 0ns, and code 1111 is 15ns. Default is 0000 = 0ns. This is used to adjust setup and hold times of the output, for the ASIC chip. DelayB[7:4] - Controls the BSAMP_LEADING_EDGE_DLY. These bits set the delay for the leading edge of the internal BSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns. DelayB[3:0] - Controls the BSAMP_TRAILING_EDGE_DLY. These bits set the delay for the trailing edge of the internal BSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns. DelayC[7:4] - Controls the VSAMP_LEADING_EDGE_DLY. These bits set the delay for the leading edge of the internal VSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns. DelayC[3:0] - Controls the VSAMP_TRAILING_EDGE_DLY. These bits set the delay for the trailing edge of the internal VSAMP pulse. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns. DelayD[7:4] - Controls the VSAMP_OGI_DLY. These bits set the delay for the internal VSAMP that is used to transfer the OGI register data to the PGA & OFFSET control registers. DelayD[3:0] - Controls the ADC_DLY. These bits set the delay of the internal clock used for ADC operation. Code 0000 is no delay. The delay increases by 0.5 ns per step to a total of 7.5 ns. Default is 0000 = 0ns.
24
xr
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
Mode Register
MODES of operation (10100) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NOFS2
TEST ENABLE
GAIN SELECT
CCD/CIS
CHAN [1]
CHAN [0]
APOAM
GOM
0
0
0
0
0
0
0
1
NOFS2 - No full scale divided by 2. Test Enable - Do not modify. Gain Select - Gain range is 1-10 for Gain Select = 0, and 2-20 for Gain Select = 1.
CCD mode is selected if CCD/CIS is 0, CIS mode is selected if CCD/CIS is 1. Three channel is selected if CHAN[1] = 0 and CHAN[0] = 0. One channel red is selected if CHAN[1] = 0 and CHAN[0] = 1. One channel green is selected if CHAN[1] = 1 and CHAN[0] = 0. One channel blue is selected if CHAN[1] = 1 and CHAN[0] = 1. The Alternate Pixel Adjust Mode is selected by setting APOAM to 1. It is used only in Fixed Gain mode i.e. with GOM=0. The GOM (gain offset mode) bit is used to select either Fixed Gain Offset Mode (GOM=0) or Pixel by Pixel Gain Offset Mode (GOM=1).
TEST TEST
(10101) default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
Test register used for factory test only. Do not modify
25
XRD9836
xr
16-BIT PIXEL GAIN AFE
REV. 1.0.0
TIMING DIAGRAMS
tap tap
X
CCDIN
X
LCLMP tcp3 taclk3 taclk3
ADCLK
tvfcr BSAMP tpwb tpwv tstl VSAMP tbvf tcr3 Clamp (Internal to XRD9836) tvbf
FIGURE 17. 3-CHANNEL CDS MODE (ALL POLARITY BITS =0)
tap
tap
CCDIN
LCLMP tcp1 taclk1 ADCLK tvfcr tpwb taclk1
tbfcr
BSAMP tstl
VSAMP tcr1 tpwv tvbf tbvf
Clamp (Internal to XRD9836)
FIGURE 18. 1-CHANNEL CDS MODE (ALL POLARITY BITS=0)
26
xr
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
tap
CIS tcp3 taclk3 taclk3 tvfcr
ADCLK tstl VSAMP tcr3 tpwv
FIGURE 19. 3-CHANNEL CIS MODE (ALL POLARITY BITS = 0, CCD/CIS BIT = 1)
tap
CIS tcp1 taclk1 taclk1
ADCCLK tstl VSAMP tpwv tcr1 tvfcr
FIGURE 20. 1-CHANNEL CIS MODE (ALL POLARITY BITS = 0, CCD/CIS BIT = 1)
27
XRD9836
xr
16-BIT PIXEL GAIN AFE
REV. 1.0.0
Pixel (n) GAIN & OFFSET
RRGGBB EERRL L DDNNUU G G G aOaOaO ififif nfnfnf
OGI 10bit parallel IE Tev
Todih
CCDOUT (Parallel RGB) BSAMP VSAMP
Pixel (n-1)
Pixel (n)
Pixel (n+1)
Pixel (n+2)
Pixel (n+3)
Pixel (n+4)
Pixel (n+5)
Tva
CDS samples Red, Green, and Blue
ADCLK Red Pixel (n+1) ADC Samples Red ADC Samples Green ADC Samples Blue tlat (9 ADCLK Latency)
ADCDO 8-bit parallel
R RGGBB DDDDDD HLHL HL
Tadcdo
FIGURE 21. 3-CHANNEL LATENCY FOR PARALLEL ADCDO (OUTPUT DATA BUS) & OGI (INPUT BUS)
OGI 10bit parallel IE
Gain (n)
Offset (n)
Gain (n+1)
Offset (n+1)
Gain (n+2)
Offset (n+2)
Gain (n+3)
Offset (n+3)
Gain (n+4)
Offset (n+4)
Gain (n+5)
Offset (n+5)
Gain (n+6)
Offset (n+6)
Gain (n+7)
Offset (n+7)
Gain (n+8)
Offset (n+8)
Gain (n+9)
Offset (n+9)
Gain (n+10)
Offset (n+10)
Grn Pixel (n+1)
Gain (n+11) Offset (n+11)
Blu Pixel (n-1)
Red Pixel (n)
Grn Pixel (n)
Tev
Togih
CCDOUT (Parallel RGB) BSAMP VSAMP
Pixel (n-1)
Pixel (n)
Pixel (n+1)
Pixel (n+2)
Pixel (n+3)
Pixel (n+4)
Pixel (n+5)
Pixel (n+6)
Pixel (n+7)
Pixel (n+8)
Blu Pixel (n)
Pixel (n+9)
Pixel (n+10)
Tva
CDS samples input
ADCLK
tlat (9 ADCLK Latency)
Pixel (n-1) Pixel (n)
ADCDO 8-bit parallel Tadcdo
MSB's
DH(n-1)
LSB's
DL(n-1)
MSB's
DH(n)
LSB's
DL(n)
FIGURE 22. 1-CHANNEL LATENCY FOR PARALLEL ADCDO (OUTPUT DATA BUS) & OGI (INPUT BUS)
28
xr
APPLICATION NOTES AND SCHEMATICS
See Figure 23 for a typical CCD application hookup. The diagram shows an interface to a standard 3 channel output CCD. Both the ADC Output and OGI Control are parallel interfaces to the system ASIC controller. The timing inputs are provided by the system ASIC or timing generator (TG). The serial port control is typically sourced from a micro processor or the system ASIC. It is recommended that all AGND, DGND and OGND pins, be connected to the analog ground plane under
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
the XRD9836. All VDD's should be supplied from a low noise, well filtered regulator which derives the power supply voltage from the CCD power supply. All of the AVDD pins are analog power supplies and should be decoupled locally to the nearest ground pin with at 0.1uF, high frequency capacitor. The DVDD and OVDD power pins should be locally decoupled to the nearest ground pin also. DVDD and OVDD should be connected to the same power supply network as the digital ASCI which receives data from the XRD9836.
15V VDD3A VDD3D
0.1uf
1uf
It is recommended that each power pin be decoupled to ground with capacitors placed as close to power pin as possible.
1nf
CCD
RED+ REDGRN+
1nf 1nf 1nf 1nf 1nf
A V D D
A V D D
A V D D
D V D D
O V D D
O V D D ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0
GRNBLU+ BLU-
ADC OUTPUT BUS
9836
REXT 10K
OGI9 OGI8 OGI7 OGI6 OGI5 OGI4 OGI3 OGI2 OGI1 OGI0 IE
ASIC OGI CONTROL
ADCCLKK TG (timing generator) VSAMP BSAMP LCLMP CAPN ASIC LOAD SCLK SDIO CMREF CAPP 2.2uf 0.1uf 2.2uf 0.1uf
A G N D
A G N D
A G N D
D G N D
O G N D
O G N D
2.2uf
0.1uf
2.2uf
0.1uf
FIGURE 23. TYPICAL CCD APPLICATION DIAGRAM FOR THE XRD9836 The XRD9836 has an input range limitation of 1V maximum for a CCD input. If the maximum CCD output signal swing is greater than 1V, a resisitive divider network on the inputs can be used to reduce the CCD output to meet the 1V input max requirement of the XRD9836 inputs. See Figure 24 for a typical implementation of a resistor divider. Each input channel will require a matching divider network.
CCD
15V
Vin
R1 R2 C1 1nf
XRD9836
RED+
Vsig
C2 1nf RED -
Vin = Vsig (R1/(R1+R2))
FIGURE 24. INPUT RESISTIVE DIVIDER NETWORK 29
XRD9836
xr
16-BIT PIXEL GAIN AFE
REV. 1.0.0
Supply Current vs. Temperature
115 VDD = 3.3V Fs = 30MHz 3-Channel Mode 105
Idd(mA)
95
85
75 -5 5 15 25 35 Temperature(C) 45 55 65 75
FIGURE 25. XRD9836 TYPICAL IDD VS TEMPERTURE
9836 System DNL 2
1.5
1
Dnl (lsb)
0.5
0
-0.5
-1
-1.5 0 8192 16384 24576 32768 Code 40960 49152 57344 65536
FIGURE 26. TYPICAL XRD9836 DNL FOR RED CHANNEL IN 3-CH MODE
30
xr
PACKAGE DRAWING:
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
31
xr
XRD9836 1.0.0
16BIT PIXEL GAIN AFE 8/15/03
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2003 EXAR Corporation Datasheet June 2003. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 32

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